The AXI Memory Mapped to PCI Express core conforms to strict PCIe transaction ordering rules. See the PCIe v2.1 Specification [Ref 8] for the complete rule set. The following behaviors are implemented in the AXI Memory Mapped to PCI Express core to enforce the PCIe transaction ordering rules on the highly-parallel AXI bus of the bridge. The rules are enforced without regard to the Relaxed Ordering attribute bit within the TLP header:
• The bresp to the remote (requesting) AXI4 master device for a write to a remote PCIe device is not issued until the MemWr TLP transmission is guaranteed to be sent on the PCIe link before any subsequent TX-transfers.
• A remote AXI master read of a remote PCIe device is not permitted to pass any previous or simultaneous AXI master writes to a remote PCIe device that occurs previously or at the same time. Timing is based off the AXI arvalid signal timing relative to the AXI awvalid . Any AXI write transaction in which awvalid was asserted before or at the same time as the arvalid for a read from PCIe is asserted causes the MemRd TLP(s) to be held until the pipelined or simultaneous MemWr TLP(s) have been sent.
• A remote PCIe device read of a remote AXI slave is not permitted to pass any previous remote PCIe device writes to a remote AXI slave received by the AXI Memory Mapped to PCI Express core. The AXI read address phase is held until the previous AXI write transactions have completed and bresp has been received for the AXI write transactions.
• Read completion data received from a remote PCIe device are not permitted to pass any remote PCIe device writes to a remote AXI slave received by the AXI Memory Mapped to PCI Express core prior to the read completion data. The bresp for the AXI write(s) must be received before the completion data is presented on the AXI read data channel.
• Read data from a remote AXI slave is not permitted to pass any remote AXI master writes to a remote PCIe device initiated on the AXI bus prior to or simultaneously with the read data being returned on the AXI bus. Timing is based on the AXI awvalid signal timing relative to the AXI rvalid assertion. Any AXI write transaction in which awvalid was asserted before or simultaneously with the rvalid being asserted up to and including the last data beat, causes the Completion TLP(s) to be held until the pipelined or simultaneous MemWr TLP(s) have been sent.
IMPORTANT: The transaction ordering rules for PCIe might have an impact on data throughput in heavy bidirectional traffic.