Some additional components to this system in the Vivado IP integrator can include the need to connect the MicroBlaze™ processor or Zynq ™ device Arm ® processor peripheral to communicate with PCI Express (in addition to the AXI4-Lite register port on the PCIe bridge). The AXI Interconnect provides this capability and performs the necessarily conversions for the various AXI ports that might be connected to the AXI Interconnect IP (described in [Ref 9] ).
The AXI Memory Mapped to PCI Express core can be configured with each port connection for an AXI Vivado IP integrator system topology. When instantiating the core, ensure the following bus interface tags are defined.
BUS_INTERFACE M_AXI
BUS_INTERFACE S_AXI
BUS_INTERFACE S_AXI_CTL