Simulation Design Overview - 2.9 English

For the simulation design, transactions are sent from the Root Port Model to the AXI Memory Mapped to PCI Express core configured as an Endpoint and processed inside the AXI Block RAM controller design.

This Figure illustrates the simulation design provided with the AXI Memory Mapped to PCI Express core.

Figure 5-1: Example Design Block Diagram

X-Ref Target - Figure 5-1

Note: The example design supports Verilog as the target language.