Shared GT_COMMON - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

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2.9 English

A quad phase-locked loop (QPLL) in GT_COMMON can serve a quad of GT_CHANNEL instances. If the PCIe core is configured as X1 or X2 and is using a QPLL, the remaining GT_CHANNEL instances can be used by other cores by sharing the same QPLL and GT_COMMON.

To share GT_COMMON instances, select Include Shared Logic (Transceiver GT_COMMON) in example design option in the Shared Logic tab ( This Figure ).

When this feature is selected, the GT_COMMON instance is removed from the pipe wrappers and is moved into the support wrapper of the example design. It also brings out additional ports to the top level to enable sharing of the GT_COMMON.

Shared logic feature for GT_COMMON helps save FPGA resources and also eases dedicated clock routing within the single GT Quad.