Shared Clocking - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

To use the share clocking feature, select Include Shared Logic (Clocking) in example design option in the Shared Logic tab ( This Figure ).

When this feature is selected, the mixed-mode clock manager (MMCM) instance is removed from the pipe wrappers and is moved into the support wrapper of the example design. It also brings out additional ports to the top level to enable sharing of the clocks.

You also have the option to modify and use the unused outputs of the MMCM.

Figure 3-3: Shared Clocking

X-Ref Target - Figure 3-3

viv_shared_clocking_axipcie.PNG

The MMCM generates the following clocks for PCIe solution wrapper:

clk_125mhz : 125 MHz clock.

clk_250mhz : 250 MHz clock.

userclk : 62.5 MHz/125 MHz/250 MHz clock, depending on selected PCIe core lane width, link speed, and AXI interface width.

userclk2 : 250 MHz/500 MHz clock, depending on selected PCIe core link speed.

oobclk : 50 MHz clock.

The other cores/logic present in the user design can use any of the MMCM outputs listed above.

The MMCM instantiated in the PCIe example design has two unconnected outputs: clkout5 , and clkout6 . You can use those outputs to generate other desired clock frequencies by selecting the appropriate CLKOUT5_DIVIDE and CLKOUT6_DIVIDE parameters for MMCM.

TIP: Sharing the MMCM between PCIe and other cores in your design saves FPGA resources and eases output clock path routing.