S AXI DATA WIDTH - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

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2.9 English

Sets the data bus width for the AXI Slave interface. This can be 64-bit or 128-bit based on your requirements. For X4G2 and X8G1, the core supports only 128-bit to achieve maximum performance.