The Root Port MSI Base register 2 (described in Table: Root Port MSI Base Register 2 ) sets the address window in Root Port cores used for MSI interrupts. MemWr TLPs to this address are interpreted as MSI interrupts. MSI TLPs are interpreted based on the address programmed in this register. For EP configurations, a read returns zero. However, the AXI Memory Mapped to PCI Express core does not support MSI-X.