Root Port Interrupt FIFO Read Register 2 (Offset 0x15C) - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

Reads from this location return queued interrupt messages. Data from each read follows the format shown in Table: Root Port Interrupt FIFO Read Register 2 . For MSI interrupts, the message payload is presented in this register, while the header information is presented in the Root Port Interrupt FIFO Read 1 register. The interrupt-handling flow should be to read the Root Port Interrupt FIFO Read 1 register first, immediately followed by this register. For non-Root Port cores, reads return 0. For INTx interrupts, reads return zero.

Note: Reads are non-destructive. Removing the message from the FIFO requires a write to either this register or the Root Port Interrupt FIFO Read 1 register (write value is ignored).

Table 2-19: Root Port Interrupt FIFO Read Register 2

Bits

Name

Core Access

Reset
Value

Description

15:0

Message Data

RWC

0

Payload for MSI messages.

31:16

Reserved

RO

0

Reserved