Root Port BAR - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

During core customization in the Vivado Design Suite, select the Hide RP BAR option to force the core to return zeros when User Logic or CPU is probing the RP BAR0 register and to mask any write to this register to prevent any address from being allocated for Root Port BAR. The base address then defaults to 0x0000_0000.

When BAR 64 bit Enabled is selected, the maximum BAR size for Root Port configuration is 4 GB. This option allows all 32-bits of AXI addresses to be addressable from the PCIe link. Inherently, AXI-PCIe BAR translation is then disabled when 4 GB is selected.

BAR 0 cannot be disabled. If a system must have no BAR for Root Port and accepts all incoming packets, select Hide RP BAR , select BAR 64 bit Enabled , and set the Bar 0 size to 4 Gigabytes .

The Root Port BAR customization options in the Vivado Design Suite are found in PCIe Base Address Registers .