The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
11/24/2023 |
2.9 |
Updated Feature Summary . |
|
02/22/2021 |
2.9 |
• Added user_link_up to Port Descriptions . • Updated link speed for x8 late width in Table: Lane Width and Link Speed . • Editorial updates in IP Facts . • Updates for core v2.9 in Upgrading in the Vivado Design Suite . • Editorial updates in Hardware Debug . |
|
04/04/2018 |
2.8 |
• Included specific list of Artix 7 devices that are not supported (IP Facts). • Added more detail to interrupt_out port description (in the Top-Level Interface Signals table in the Product Specification chapter). • Changed C_PCIE2AXIBAR_n to C_PCIEBAR2AXIBAR_n (in the BAR and Address Translation section in the Designing with the Core chapter). |
|
10/04/2017 |
2.8 |
• Updated axi_aresetn description in Top-Level Interface Signals table. • Updated Bit[3] description in Interrupt Decode Register table. • Added Important note for Device ID in Design Flow Steps chapter. |
|
04/05/2017 |
2.8 |
• Updated to latest 2017.1 release. • Added Additional Debug Options section in Design Flow Steps chapter. • Added en_jtag_debug in Parameter Changes table in Upgrading appendix. |
|
11/30/2016 |
2.8 |
Updated to latest 2016.4 release. |
|
10/05/2016 |
2.8 |
• Updated the Root Port MSI Base Register 2 (Offset 0x150) section (Parameter Dependencies) in Chapter 2. |
|
06/08/2016 |
2.8 |
• Removed MSI-X support in document. • Updated Fig. 4-4: PCIe Base Address Register. |
|
04/06/2016 |
2.8 |
• Small editorial update to the Root Port Error FIFO Read Register (Offset 0x154) section. • Added the Intercept and Decode Incoming MSI Packet customization option (PCIe Miscellaneous tab). • Updated the description for the following customization options: ° Base Address Register Overview (AXI BARs tab) ° 64-bit Enable (AXI BARs tab) ° AXI to PCIe Translation (AXI BARs tab) • Changed text because I/O BARs are no longer supported. • Added parameter and port changes to the Migrating and Upgrading appendix. |
|
09/30/2015 |
2.7 |
• Added MSI-X and multiple vector address (only single MSI is supported) to Unsupported Features list. • Added the C_MSI_DECODE_ENABLE parameter. • Clarified that the component name (in Vivado IDE) cannot be same as reserved module names from core. • Updated PIPE signal mapping information with new tables: Common In/Out Commands and Endpoint PIPE Signals Mappings, and Input/Output Bus with Endpoint PIPE Signals Mapping. |
|
06/24/2015 |
2.6 |
• Moved performance and resource utilization data to www.xilinx.com. • Updated footnote details for top-level interface signal m_axi_arsixe[2:0]. • Corrected the documented clocking interface signal names. • Updated the documented sequence to clear correctable, non-fatal, and fatal bits of the Interrupt Decode Register. • Added the Root Port BAR section. • Added the BAR Addressing section. • Added the Enable External PIPE Interface option to Vivado IDE options, and added more information about PIPE Mode simulation support. • Updated Vivado Lab Edition to Vivado Design Suite Debug Feature. • Added new parameter migration information. |
|
04/01/2015 |
2.6 |
• Changed document title to match core name in Vivado IP catalog. • Added further clarifying footnotes to Line Rate for PCIe Support for Gen1/Gen2 table. • Added the pipe_txinhibit signal. • Added Test Bench design details. • Updated Vivado lab tools to Vivado Lab Edition. |
|
11/19/2014 |
2.5 |
• Correction made to 64-bit BAR size range upper limit. • Updated the simulation procedures for Cadence Incisive Enterprise Simulator (IES), and Verilog Compiler Simulator (VCS). • Added Important Note regarding the recommended version of Mentor Graphics Questa SIM to use to avoid simulation failure. • Minor change made to debug diagrams. |
|
10/01/2014 |
2.5 |
Updated for core v2.5. |
|
06/02/2014 |
2.4 |
• Updated for core v2.4. • Added new device support. • Removed the axi_aclk and axi_ctl_aclk input ports. |
|
04/02/2014 |
2.3 |
• Updated simulation information. • Minor changes and updates. |
|
12/18/2013 |
2.3 |
• Updated for core v2.3. • Updated Example Design chapter. • Updated parameter changes and port changes in Migrating and Updating chapter. |
|
10/02/2013 |
2.2 |
• Updated for core v2.2. • Updated resource utilization numbers. • Added information about the Shared Logic feature. • Added example design information. • Added port and parameter upgrade information. • Added transceiver debug information. |
|
03/20/2013 |
2.0 |
Updated for core v2.0, and for Vivado Design Suite-only support. |
|
12/18/2012 |
1.2 |
• Updated core v1.06a, ISE Design Suite 14.4, and Vivado Design Suite 2012.4. • Updated Customizing and Generating the Core . • Added Debugging . |
|
10/16/2012 |
1.1 |
• Updated core v1.05a, ISE Design Suite 14.3, and Vivado Design Suite 2012.3. • Added Chapter 4 , Customizing and Generating the Core . • Major updates to PCIe Clock Integration. • Added Unsupported Request to Upstream Traffic and Clock Frequencies. |
|
07/25/2012 |
1.0 |
Initial Xilinx release. This release is for core version 1.04.a with ISE Design Suite 14.2 and Vivado Design Suite 2012.2. This document replaces DS820, LogiCORE IP AXI Bridge for PCI Express Data Sheet . |