The AXI Memory Mapped to PCI Express core requires a clock period constraint for the REFCLK input that agrees with the C_ REF_CLK_FREQ parameter setting. In addition, pin-placement (LOC) constraints are needed that are board/part/package specific.
See Placement Constraints for more details on the constraint paths for FPGA architectures.
Additional information on clocking can be found in the AMD Solution Center for PCI Express (see Solution Center for PCI Express ).