Port Descriptions - 2.9 English

Global Signals

refclk

I

PCIe Reference Clock

axi_aresetn

I

Global reset signal for the IP. Resets GT, PCIe, and AXI interfaces.

axi_aclk_out

O

PCIe derived clock output for axi_aclk .

axi_ctl_aclk_out

O

PCIe derived clock output for axi_ctl_aclk

mmcm_lock

O

Indicates axi_aclk_out from the axi_enhanced_pcie block is stable

interrupt_out

O

Interrupt signal. This signal is asserted for as long as there exists at least one bit asserted in the Interrupt Decode register and is not masked in the Interrupt Mask register.

user_link_up

O

This signal is asserted when the PCI Express core is linked up with a link partner PCIe device.

AXI Slave Interface

s_axi_awid[c_s_axi_id_width-1:0]

I

Slave write address ID

s_axi_awaddr[ c_s_ axi_addr_width-1:0]

I

Slave write address

s_axi_awregion[3:0]

I

Slave write region decode

s_axi_awlen[7:0]

I

Slave write burst length

s_axi_awsize[2:0]

I

Slave write burst size

s_axi_awburst[1:0]

I

Slave write burst type

s_axi_awvalid

I

Slave address write valid

s_axi_awready

O

Slave address write ready

s_axi_wdata[ c_s_ axi_data_width-1:0]

I

Slave write data

s_axi_wstrb[ c_s_ axi_data_width/8-1:0]

I

Slave write strobe

s_axi_wlast

I

Slave write last

s_axi_wvalid

I

Slave write valid

s_axi_wready

O

Slave write ready

s_axi_bid[c_s_axi_id_width-1:0]

O

Slave response ID

s_axi_bresp[1:0]

O

Slave write response

s_axi_bvalid

O

Slave write response valid

s_axi_bready

I

Slave response ready

s_axi_arid[c_s_axi_id_width-1:0]

I

Slave read address ID

s_axi_araddr[ c_s_ axi_addr_width-1:0]

I

Slave read address

s_axi_arregion[3:0]

I

Slave read region decode

s_axi_arlen[7:0]

I

Slave read burst length

s_axi_arsize[2:0]

I

Slave read burst size

s_axi_arburst[1:0]

I

Slave read burst type

s_axi_arvalid

I

Slave read address valid

s_axi_arready

O

Slave read address ready

s_axi_rid[c_s_axi_id_width-1:0]

O

Slave read ID tag

s_axi_rdata[ c_s_ axi_data_width-1:0]

O

Slave read data

s_axi_rresp[1:0]

O

Slave read response

s_axi_rlast

O

Slave read last

s_axi_rvalid

O

Slave read valid

s_axi_rready

I

Slave read ready

AXI Master Interface

m_axi_awaddr[ c_m_ axi_addr_width-1:0]

O

Master write address

m_axi_awlen[7:0]

O

Master write burst length

m_axi_awsize[2:0]

O

Master write burst size

m_axi_awburst[1:0]

O

Master write burst type

m_axi_awprot[2:0]

O

Master write protection type

m_axi_awvalid

O

Master write address valid

m_axi_awready

I

Master write address ready

m_axi_wdata[ c_m_ axi_data_width-1:0]

O

Master write data

m_axi_wstrb[ c_m_ axi_data_width/8-1:0]

O

Master write strobe

m_axi_wlast

O

Master write last

m_axi_wvalid

O

Master write valid

m_axi_wready

I

Master write ready

m_axi_bresp[1:0]

I

Master write response

m_axi_bvalid

I

Master write response valid

m_axi_bready

O

Master response ready

m_axi_araddr[ c_m_ axi_addr_width-1:0]

O

Master read address

m_axi_arlen[7:0]

O

Master read burst length

m_axi_arsize[2:0] ⁽¹⁾

O

Master read burst size

m_axi_arburst[1:0]

O

Master read burst type

m_axi_arprot[2:0]

O

Master read protection type

m_axi_arvalid

O

Master read address valid

m_axi_arready

I

Master read address ready. This signal only responds when Bus Master Enable bit is set in the Command register within PCI Configuration Space.

m_axi_rdata[ c_m_ axi_data_width-1:0]

I

Master read data

m_axi_rresp[1:0]

I

Master read response

m_axi_rlast

I

Master read last

m_axi_rvalid

I

Master read valid

m_axi_rready

O

Master read ready

AXI4-Lite Control Interface

s_axi_ctl_awaddr[31:0]

I

Slave write address

s_axi_ctl_awvalid

I

Slave write address valid

s_axi_ctl_awready

O

Slave write address ready

s_axi_ctl_wdata[31:0]

I

Slave write data

s_axi_ctl_wstrb[3:0]

I

Slave write strobe

s_axi_ctl_wvalid

I

Slave write valid

s_axi_ctl_wready

O

Slave write ready

s_axi_ctl_bresp[1:0]

O

Slave write response

s_axi_ctl_bvalid

O

Slave write response valid

s_axi_ctl_bready

I

Slave response ready

s_axi_ctl_araddr[31:0]

I

Slave read address

s_axi_ctl_arvalid

I

Slave read address valid

s_axi_ctl_arready

O

Slave read address ready

s_axi_ctl_rdata[31:0]

O

Slave read data

s_axi_ctl_rresp[1:0]

O

Slave read response

s_axi_ctl_rvalid

O

Slave read valid

s_axi_ctl_rready

I

Slave read ready

MSI Signals

intx_msi_request

I

Legacy interrupt input (see c_interrupt_pin ) when msi_enable = 0.

Initiates a MSI write request when msi_enable = 1.

Intx_msi_request is asserted for one clock period.

intx_msi_grant

O

Indicates legacy interrupt/MSI grant signal. The intx_msi_grant signal is asserted for one clock period when the interrupt is accepted by the PCIe core.

msi_enable

O

Indicates when MSI is enabled.

msi_vector_num [4:0]

I

Indicates MSI vector to send when writing a MSI write request.

msi_vector_width [2:0]

O

Indicates the size of the MSI field (the number of MSI vectors allocated to the device).

PCIe Interface

pci_exp_rxp [C_NO_OF_LANES-1:0][]

I

PCIe RX serial interface

pci_exp_rxn [C_NO_OF_LANES-1:0][]

I

PCIe RX serial interface

pci_exp_txp [C_NO_OF_LANES-1:0][]

O

PCIe TX serial interface

pci_exp_txn [C_NO_OF_LANES-1:0][]

O

PCIe TX serial interface

Notes:

1. When a read request is received with a length that is not 1DW and is shorter than the Master AXI data width, m_axi_arsize always indicates that the requested size is equal to the Master AXI data width. The core drops the extra data when a completion packet is formed and sent back to the requester.