Placement Constraints - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

The AXI Memory Mapped to PCI Express core provides a Xilinx design constraint (XDC) file for all supported PCIe, Part, and Package permutations. You can find the generated XDC file in the Sources tab of the Vivado IDE after generating the IP in the Customize IP dialog box.

For design platforms, it might be necessary to manually place and constrain the underlying blocks of the AXI Memory Mapped to PCI Express core. The modules to assign a LOC constraint include:

the embedded integrated block for PCIe itself

the GTX transceivers (for each channel)

the PCIe differential clock input (if utilized)

The following subsection describes the example location constraints.