|
Generic
|
Parameter
|
Affects
|
Depends
|
Description
|
|
Bridge Parameters
|
|
G1
|
C_FAMILY
|
G2, G41, G49, G55
|
|
|
|
G2
|
C_INCLUDE_RC
|
|
G1
|
|
|
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C_MSI_DECODE_ENABLE
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G2
|
TRUE: Allows the bridge to decode incoming MSI packet.
FALSE: Ignore incoming MSI packet and treats it as a regular Memory Write packet.
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|
G3
|
C_COMP_TIMEOUT
|
|
|
|
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G4
|
C_INCLUDE_BAROFFSET_REG
|
G10,
G14,
G18,
G22,
G26, G30
|
G6
|
If G4 = 0, then G10, G14, G18, G22, G26 and G30 have no meaning. The number of registers included is set by G6.
|
|
G5
|
C_SUPPORTS_NARROW_
BURST
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|
|
|
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G6
|
C_AXIBAR_NUM
|
G4,
G7 - G30
|
|
If G6 = 1, then G7 - G10 are enabled.
If G6 = 2, then G7 - G14 are enabled.
If G6 = 3, then G7 - G18 are enabled.
If G6 = 4, then G7 - G22 are enabled.
If G6 = 5, then G7 - G26 are enabled.
If G6 = 6, then G7 - G30 are enabled.
|
|
G7
|
C_AXIBAR_0
|
G8
|
G6, G8
|
G7 and G8 define the range in AXI memory space that is responded to by this device (AXIBAR)
|
|
G8
|
C_AXIBAR_HIGHADDR_0
|
G7
|
G6, G7
|
G7 and G8 define the range in AXI memory space that is responded to by this device (AXIBAR)
|
|
G9
|
C_AXIBAR_AS_0
|
|
G6
|
|
|
G10
|
C_AXIBAR2PCIEBAR_0
|
|
G4, G6
|
Meaningful when G4 = 1.
|
|
G11
|
C_AXIBAR_1
|
G12
|
G12
|
G11 and G12 define the range in AXI-memory space that is responded to by this device (AXIBAR)
|
|
G12
|
C_AXIBAR_HIGHADDR_1
|
G11
|
G6, G11
|
G11 and G12 define the range in AXI-memory space that is responded to by this device (AXIBAR)
|
|
G13
|
C_AXIBAR_AS_1
|
|
G6
|
|
|
G14
|
C_AXIBAR2PCIEBAR_1
|
|
G4, G6
|
Meaningful when G4 = 1.
|
|
G15
|
C_AXIBAR_2
|
G16
|
G16
|
G15 and G16 define the range in AXI-memory space that is responded to by this device (AXIBAR)
|
|
G16
|
C_AXIBAR_HIGHADDR_2
|
G15
|
G6, G15
|
G15 and G16 define the range in AXI-memory space that is responded to by this device (AXIBAR)
|
|
G17
|
C_AXIBAR_AS_2
|
|
G6
|
|
|
G18
|
C_AXIBAR2PCIEBAR_2
|
|
G4, G6
|
Meaningful when G4 = 1.
|
|
G19
|
C_AXIBAR_3
|
G20
|
G20
|
G19 and G20 define the range in AXI-memory space that is responded to by this device (AXIBAR)
|
|
G20
|
C_AXIBAR_HIGHADDR_3
|
G19
|
G6, G19
|
G19 and G20 define the range in AXI-memory space that is responded to by this device (AXIBAR)
|
|
G21
|
C_AXIBAR_AS_3
|
|
G6
|
|
|
G22
|
C_AXIBAR2PCIEBAR_3
|
|
G4, G6
|
Meaningful when G4 = 1.
|
|
G23
|
C_AXIBAR_4
|
G24
|
G24
|
G23 and G24 define the range in AXI-memory space that is responded to by this device (AXIBAR)
|
|
G24
|
C_AXIBAR_HIGHADDR_4
|
G23
|
G6, G23
|
G23 and G24 define the range in AXI-memory space that is responded to by this device (AXIBAR)
|
|
G25
|
C_AXIBAR_AS_4
|
|
G6
|
|
|
G26
|
C_AXIBAR2PCIEBAR_4
|
|
G4, G6
|
Meaningful if G4 = 1.
|
|
G27
|
C_AXIBAR_5
|
G28
|
G28
|
G27 and G28 define the range in AXI-memory space that is responded to by this device (AXIBAR)
|
|
G28
|
C_AXIBAR_HIGHADDR_5
|
G27
|
G6, G27
|
G27 and G28 define the range in AXI-memory space that is responded to by this device (AXIBAR)
|
|
G29
|
C_AXIBAR_AS_5
|
|
G6
|
|
|
G30
|
C_AXIBAR2PCIEBAR_5
|
|
G4, G6
|
Meaningful if G4 = 1.
|
|
G31
|
C_PCIEBAR_NUM
|
G33-G38
|
|
If G31 = 1, then G32, G33 are enabled.
If G31 = 2, then G32 - G36 are enabled.
If G31 = 3, then G32 - G38 are enabled
|
|
G32
|
C_PCIEBAR_AS
|
|
|
|
|
G33
|
C_PCIEBAR_LEN_0
|
G34
|
G31
|
|
|
G34
|
C_PCIEBAR2AXIBAR_0
|
|
G31, G33
|
Only the high-order bits above the length defined by G33 are meaningful.
|
|
G35
|
C_PCIEBAR_LEN_1
|
G36
|
G31
|
|
|
G36
|
C_PCIEBAR2AXIBAR_1
|
|
G31, G35
|
Only the high-order bits above the length defined by G35 are meaningful.
|
|
G37
|
C_PCIEBAR_LEN_2
|
G38
|
G31
|
|
|
G38
|
C_PCIEBAR2AXIBAR_2
|
|
G31, G37
|
Only the high-order bits above the length defined by G37 are meaningful.
|
|
Core for PCIe Configuration Parameters
|
|
G41
|
C_NO_OF_LANES
|
|
G1, G50, G53
|
|
|
G42
|
C_DEVICE_ID
|
|
|
|
|
G43
|
C_VENDOR_ID
|
|
|
|
|
G44
|
C_CLASS_CODE
|
|
|
|
|
G45
|
C_REV_ID
|
|
|
|
|
G46
|
C_SUBSYSTEM_ID
|
|
|
|
|
G47
|
C_SUBSYSTEM_VENDOR_ID
|
|
|
|
|
G48
|
C_PCIE_CAP_SLOT_
IMPLEMENTED
|
|
G2
|
If G2 = 0, G48 is not meaningful
|
|
G49
|
C_REF_CLK_FREQ
|
|
G1
|
|
|
Memory-Mapped AXI4 Bus Parameters
|
|
G50
|
C_M_AXI_DATA_WIDTH
|
G53
|
G1, G41, G53
|
G50 must be equal to G53
|
|
G51
|
C_M_AXI_ADDR_WIDTH
|
G54
|
G54
|
G51 must be equal to G54
|
|
G52
|
C_S_AXI_ID_WIDTH
|
|
|
|
|
G53
|
C_S_AXI_DATA_WIDTH
|
G50
|
G1, G41, G50
|
G53 must be equal to G50
|
|
G54
|
C_S_AXI_ADDR_WIDTH
|
G51
|
G51
|
G54 must be equal to G51
|
|
G55
|
C_MAX_LINK_SPEED
|
|
G1
|
|
|
G56
|
C_INTERRUPT_PIN
|
|
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