Parameter Changes - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

Table: Parameter Changes shows the changes to parameters in the current version of the core.

Table A-1: Parameter Changes

User Parameter Name

Display Name

New/Change/Removed

Details

Default Value

PCIE_CAP_SLOT_IMPLEMENTED

Enable Slot Clock Configuration

Removed

Removed this parameter and added a new one.

NA

SLOT_CLOCK_CONFIG

Enable Slot Clock Configuration

Added

Added this parameter in place of PCIE_CAP_SLOT_IMPLEMENTED.

true (Checked)

BASE_CLASS_MENU

Base Class Menu

Changed

Changed the default value.

Memory controller

SUB_CLASS_INTERFACE_MENU

Sub Class Interface Menu

Changed

Changed the default value.

Other memory controller

en_jtag_debug

Enable JTAG Debugger

New

Added the parameter to enable the JTAG Debug option Unchecked.

Unchecked

REDUCE_OOB_FREQ

Reduce OOB Frequency

Added

Added the parameter to reduce OOB frequency

false