PIPE Mode Simulations

PIPE Mode Simulations - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID

PG055

Release Date

2023-11-24

Version

2.9 English

The PIPE Simulation mode allows you to run the simulations without serial transceiver block to speed up simulations. To run the simulations using the PIPE interface to speed up the simulation, generate the core after selecting the Enable External PIPE Interface option in the Basic tab of the Customize IP dialog box.

For details, see Enable External PIPE Interface . For third-party bus functional model support, see the PIPE Mode Simulation Using Integrated Endpoint PCI Express Block in Gen2 x8 Configurations Application Note (XAPP1184) [Ref 16] .

Third-party simulation support pulls out the following ports when Enable External PIPE interface ports is selected. The following tables describe the ports that add to the boundary of the AXI PCIe core when this option is selected.

For PIPE ports to and from the pcie_top, each lane has independent input and output bus signals.

Table: Common Input/Output Commands with Endpoint PIPE Signals Mapping and Table: Input/Output Bus with Endpoint PIPE Signals Mapping describe the PIPE bus signals available at the top level of the core and their corresponding mapping inside the EP core (pcie_top) PIPE signals.

IMPORTANT: A new file, xil_sig2pipe.v , is delivered in the simulation directory, and the file replaces phy_sig_gen.v . BFM/VIPs should interface with the xil_sig2pipe instance in board.v .

Table 4-4: Common Input/Output Commands with Endpoint PIPE Signals Mapping
In Commands	Endpoint PIPE Signals Mapping	Out Commands	Endpoint PIPE Signals Mapping
common_commands_in[3:0]	not used ⁽¹⁾	common_commands_out[0]	pipe_clk ⁽²⁾
		common_commands_out[1]	pipe_tx_rate_gt ⁽³⁾
		common_commands_out[2]	pipe_tx_rcvr_det_gt
		common_commands_out[3]	pipe_tx_deemph_gt
		common_commands_out[6:4]	pipe_tx_margin_gt
		common_commands_out[11:7]	not used ⁽¹⁾
Notes: 1. These ports functionality has been deprecated and can be left unconnected. 2. pipe_clk is an output clock based on the core configuration. For Gen1 rate, pipe_clk is 125 MHz. For Gen2, pipe_clk is 250 MHz. 3. pipe_tx_rate_gt indicates the pipe rate: 1’b0 for Gen1, and 1’b1 for Gen2.

Table 4-5: Input/Output Bus with Endpoint PIPE Signals Mapping
Input Bus	Endpoint PIPE Signals Mapping	Output Bus	Endpoint PIPE Signals Mapping
pipe_rx_0_sigs[15:0]	pipe_rx0_data_gt	pipe_tx_0_sigs[15: 0]	pipe_tx0_data_gt
pipe_rx_0_sigs[17:16]	pipe_rx0_char_is_k_gt	pipe_tx_0_sigs[17:16]	pipe_tx0_char_is_k_gt
pipe_rx_0_sigs[18]	pipe_rx0_elec_idle_gt	pipe_tx_0_sigs[18]	pipe_tx0_elec_idle_gt
pipe_rx_0_sigs[24:19]	not used ⁽¹⁾	pipe_tx_0_sigs[19]	pipe_tx0_compliance_gt
		pipe_tx_0_sigs[20]	pipe_rx0_polarity_gt
		pipe_tx_0_sigs[22:21]	pipe_tx0_powerdown_gt
Notes: 1. This ports functionality has been deprecated and can be left unconnected. 2. Lanes 1 to 7 use similar signal definitions.