PCIe Configuration Space Header - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

The PCIe Configuration Space Header is a memory aperture for accessing the core for PCIe configuration space. For 7 series devices, this area is read-only when configured as an Endpoint. Writes are permitted for some registers when a 7 series device is configured as a Root Port. Special access modes can be enabled using the PHY Status/Control register. All reserved or undefined memory-mapped addresses must return zero and writes have no effect.