PCIe Clock Integration - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

The PCIe differential clock input in the system might need to use a differential input buffer (that is instantiated separately) from the AXI Memory Mapped to PCI Express core. The Vivado IP integrator automatically inserts the appropriate clock buffer.