PCIe Base Address Registers - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

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2.9 English

The PCIe Base Address Registers (BARs) screen shown in This Figure set the base address register space for the Endpoint configuration. Each BAR (0 through 5) configures the BAR Aperture Size and Control attributes of the Physical Function, as described in Table: BAR Size Ranges for Device Configuration .

Figure 4-4: PCIe Base Address Register

X-Ref Target - Figure 4-4