Memory Map - 2.9 English

Memory Map - 2.9 English - PG055

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID

PG055

Release Date

2023-11-24

Version

2.9 English

The memory map shown in Table: Register Memory Map shows the address mapping for the AXI Memory Mapped to PCI Express core. These registers are described in more detail in the following section. All registers are accessed through the AXI4-Lite Control Interface and are offset from C_BASEADDR. During a reset, all registers return to default values.

Table 2-5: Register Memory Map
Accessibility	Offset	Contents	Location
RO - EP , R/W - RC	0x000 - 0x124	PCIe Configuration Space Header	Part of integrated PCIe configuration space.
RO	0x128	Vendor-Specific Enhanced Capability (VSEC) Capability	VSEC of integrated PCIe configuration space.
RO	0x12C	VSEC Header	VSEC of integrated PCIe configuration space.
RO	0x130	Bridge Info	AXI bridge defined memory-mapped register space.
RO - EP , R/W - RC	0x134	Bridge Status and Control
R/W	0x138	Interrupt Decode
R/W	0x13C	Interrupt Mask
RO - EP , R/W - RC	0x140	Bus Location
RO	0x144	Physical-Side Interface (PHY) Status/Control
RO - EP, R/W - RC	0x148	Root Port Status/Control
RO - EP, R/W - RC	0x14C	Root Port MSI Base 1
RO - EP, R/W - RC	0x150	Root Port MSI Base 2
RO - EP, R/W - RC	0x154	Root Port Error FIFO Read
RO - EP, R/W - RC	0x158	Root Port Interrupt FIFO Read 1
RO - EP, R/W - RC	0x15C	Root Port Interrupt FIFO Read 2
RO	0x160 - 0x1FF	Reserved (zeros returned on read)
RO	0x200	VSEC Capability 2
RO	0x204	VSEC Header 2
R/W	0x208 - 0x234	AXI Base Address Translation Configuration Registers	AXI bridge defined memory-mapped space.
RO	0x238 - 0xFFF	Reserved (zeros returned on read)