Sets the data bus width for the AXI Master interface. This can be 64-bit or 128-bit based on your requirement. For X4G2 and X8G1, the core supports only 128-bit to achieve maximum performance.
Sets the data bus width for the AXI Master interface. This can be 64-bit or 128-bit based on your requirement. For X4G2 and X8G1, the core supports only 128-bit to achieve maximum performance.