This section highlights the LOC constraints to be specified in the XDC file for the AXI Memory Mapped to PCI Express core for design implementations.
For placement/path information on the integrated block for PCIe itself, the following constraint can be utilized:
set_property LOC PCIE_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/pcie_top_i/pcie_7x_i/pcie_block_i}]
For placement/path information of the GTX transceivers, the following constraint can be utilized:
set_property LOC GTXE2_CHANNEL_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
For placement/path constraints of the input PCIe differential clock source (using the example provided in System Integration ), the following can be utilized:
set_property LOC IBUFDS_GTE2_X*Y* [get_cells {*/PCIe_Diff_Clk_I/USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I}]