Location Constraints for Artix 7 FPGAs - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

Special consideration must be given to Artix 7 device implementations. The same IP block constraint can be used as described previously (see Location Constraints for Virtex 7 and Kintex 7 FPGAs ). However, the PCIe serial transceiver wrapper instance is different in the IP. Use the following LOC constraint for the GTP transceivers in Artix 7 devices.

set_property LOC GTPE2_CHANNEL_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]

Also for Artix 7 devices, the GTP_COMMON must be constrained to a location. The following LOC constraint can be utilized.

set_property LOC GTPE2_COMMON_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.qpll_wrapper_i/gtp_common.gtpe2_common_i}]