Limitations - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
Release Date
2.9 English

The reset logic in the pipe wrapper resets the QPLL when the PCIe Block performs a rate change. When sharing is enabled, the core/logic which is sharing the QPLL must be able to handle and recover from this reset.

The settings of the GT_COMMON should not be changed as they are optimized for the PCIe core.

Figure 3-4: Shared GT_COMMON

X-Ref Target - Figure 3-4