The Interrupt Decode register (described in
Table: Interrupt Decode Register
) provides a single location where the host processor interrupt service routine can determine what is causing the interrupt to be asserted and how to clear the interrupt. Writing a
1'b1
to any bit of the Interrupt Decode register clears that bit except for the Correctable, Non-Fatal, and Fatal bits.
Follow this sequence to clear the Correctable, Non-Fatal, and Fatal bits:
1.
Clear the Root Port Error FIFO (0x154) by performing first a read, followed by write-back of the same register.
2.
Read Root Port Status/Control Register (0x148) bit 16, and ensure that the Error FIFO is empty.
Note:
If the error FIFO is still not empty, repeat
step 1
and
step 2
until the Error FIFO is empty.
3.
Write to the Interrupt Decode Register (0x138) with 1 to the appropriate error bit to clear it.
IMPORTANT:
An asserted bit in the Interrupt Decode register does not cause the interrupt line to assert unless the corresponding bit in the Interrupt Mask register is also set.
Table 2-10:
Interrupt Decode Register
|
Bits
|
Name
|
Core Access
|
Reset Value
|
Description
|
|
0
|
Link Down
|
RW1C
|
0
|
Indicates that Link-Up on the PCI Express link was lost. Not asserted unless link-up had previously been seen.
|
|
1
|
ECRC Error
|
RW1C
|
0
|
Indicates received packet failed ECRC check.
(Only applicable to 7 series and Zynq 7000 SoC device cores.)
|
|
2
|
Streaming Error
|
RW1C
|
0
|
Indicates a gap was encountered in a streamed packet on the TX interface (RW, RR, or CC).
|
|
3
|
Hot Reset
|
RW1C
|
0
|
Indicates a Hot Reset was detected (Only applicable to Endpoint cores).
|
|
4
|
Reserved
|
RO
|
0
|
Reserved
|
|
7:5
|
Cfg Completion Status
|
RW1C
|
0
|
Indicates config completion status.
|
|
8
|
Cfg Timeout
|
RW1C
|
0
|
Indicates timeout on an ECAM access.
(Only applicable to Root Port cores.)
|
|
9
|
Correctable
|
RW1C
|
0
|
Indicates a correctable error message was received.
Requester ID of error message should be read from the Root Port FIFO.
(Only applicable to Root Port cores.)
|
|
10
|
Non-Fatal
|
RW1C
|
0
|
Indicates a non-fatal error message was received.
Requester ID of error message should be read from the Root Port FIFO.
(Only applicable to Root Port cores.)
|
|
11
|
Fatal
|
RW1C
|
0
|
Indicates a fatal error message was received.
Requester ID of error message should be read from the Root Port FIFO.
(Only applicable to Root Port cores.)
|
|
15:12
|
Reserved
|
RO
|
0
|
Reserved
|
|
16
|
INTx Interrupt Received
|
RW1C
|
0
|
Indicates an INTx interrupt was received.
Interrupt details should be read from the Root Port FIFO.
(Only applicable to Root Port cores.)
|
|
17
|
MSI Interrupt Received
|
RW1C
|
0
|
Indicates an MSI(x) interrupt was received.
Interrupt details should be read from the Root Port FIFO.
(Only applicable to Root Port cores.)
|
|
19:18
|
Reserved
|
RO
|
0
|
Reserved
|
|
20
|
Slave Unsupported Request
|
RW1C
|
0
|
Indicates that a completion TLP was received with a status of
0b001
- Unsupported Request.
|
|
21
|
Slave Unexpected Completion
|
RW1C
|
0
|
Indicates that a completion TLP was received that was unexpected.
|
|
22
|
Slave Completion Timeout
|
RW1C
|
0
|
Indicates that the expected completion TLP(s) for a read request for PCIe was not returned within the time period selected by the C_COMP_TIMEOUT parameter.
|
|
23
|
Slave Error Poison
|
RW1C
|
0
|
Indicates the EP bit was set in a completion TLP.
|
|
24
|
Slave Completer Abort
|
RW1C
|
0
|
Indicates that a completion TLP was received with a status of 0b100 - Completer Abort.
|
|
25
|
Slave Illegal Burst
|
RW1C
|
0
|
Indicates that a burst type other than INCR was requested by the AXI master.
|
|
26
|
Master DECERR
|
RW1C
|
0
|
Indicates a Decoder Error (DECERR) response was received.
|
|
27
|
Master SLVERR
|
RW1C
|
0
|
Indicates a Slave Error (SLVERR) response was received.
|
|
28
|
Master Error Poison
|
RW1C
|
0
|
Indicates an EP bit was set in a MemWR TLP for PCIe.
|
|
31:29
|
Reserved
|
RO
|
0
|
Reserved
|