The AXI Memory Mapped to PCI Express core is an interface between the AXI4 and PCI Express. It contains the memory mapped AXI4 to AXI4-Stream Bridge and the AXI4-Stream Enhanced Interface Block for PCIe. The memory-mapped AXI4 to AXI4-Stream Bridge contains a register block and two functional half bridges, referred to as the Slave Bridge and Master Bridge. The slave bridge connects to the AXI4 Interconnect as a slave device to handle any issued AXI4 master read or write requests. The master bridge connects to the AXI4 Interconnect as a master to process the PCIe generated read or write TLPs. The core uses a set of interrupts to detect and flag error conditions.
The AXI Memory Mapped to PCI Express core supports both Root Port and Endpoint configurations.
• When configured as an Endpoint, the AXI Memory Mapped to PCI Express core supports up to three 32-bit or 64-bit PCIe Base Address Registers (BARs).
• When configured as a Root Port, the core supports a single 32-bit or 64-bit PCIe BAR.
The AXI Memory Mapped to PCI Express core is compliant with the PCI Express Base Specification v2.0 [Ref 8] and with the AMBA ® AXI Protocol Specification [Ref 7] . PCIe compliance is run with the base PCI Express IP for each silicon family. You can check the list of qualified devices at Integrators List .