Example Design Elements - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

The core wrapper includes:

An example Verilog HDL or VHDL wrapper (instantiates the cores and example design).

A customizable demonstration test bench to simulate the example design.