Example 4 - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

This example shows the generic settings to set up a combination of two independent 32-bit AXI BARs and two independent 64-bit BARs and address translation of AXI addresses to a remote address space for PCIe. This setting of AXI BARs do not depend on the BARs for PCIe within the Bridge.

In this example, where C_AXIBAR_NUM=4, the following assignments for each range are made:

C_AXIBAR_AS_0=0

C_AXIBAR_0=0x12340000

C_AXI_HIGHADDR_0=0x1234FFFF

C_AXIBAR2PCIEBAR_0=0x5671XXXX (Bits 15-0 do not matter)

C_AXIBAR_AS_1=1

C_AXIBAR_1=0xABCDE000

C_AXI_HIGHADDR_1=0xABCDFFFF

C_AXIBAR2PCIEBAR_1=0x50000000FEDC0XXX (Bits 12-0 do not matter)

C_AXIBAR_AS_2=0

C_AXIBAR_2=0xFE000000

C_AXI_HIGHADDR_2=0xFFFFFFFF

C_AXIBAR2PCIEBAR_2=0x40XXXXXX (Bits 24-0 do not matter)

C_AXIBAR_AS_3=1

C_AXIBAR_3=0x00000000

C_AXI_HIGHADDR_3=0x0000007F

C_AXIBAR2PCIEBAR_3=0x600000008765438X (Bits 6-0 do not matter)

Accessing the Bridge AXIBAR_0 with address 0x12340ABC on the AXI bus yields 0x56710ABC on the bus for PCIe.

Accessing the Bridge AXIBAR_1 with address 0xABCDF123 on the AXI bus yields 0x50000000FEDC1123 on the bus for PCIe.

Accessing the Bridge AXIBAR_2 with address 0xFFFEDCBA on the AXI bus yields 0x41FEDCBA on the bus for PCIe.

Accessing the AXI M S PCIe Bridge AXIBAR_3 with address 0x00000071 on the AXI bus yields 0x60000000876543F1 on the bus for PCIe.