Example 3 - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

This example shows the generic settings to set up two independent BARs for PCIe and address translation of addresses for PCIe to a remote AXI address space. This setting of BARs for PCIe does not depend on the AXI BARs within the bridge.

In this example, where C_PCIEBAR_NUM=2, the following range assignments are made:

BAR 0 is set to 0x20000000_ABCD8000 by the Root Port

C_PCIEBAR_LEN_0=15

C_PCIEBAR2AXIBAR_0=0x1234_0XXX (Bits 14-0 do not matter)

BAR 1 is set to 0xA000000012000000 by Root Port

C_PCIEBAR_LEN_1=25

C_PCIEBAR2AXIBAR_1=0xFEXXXXXX (Bits 24-0 do not matter)

Accessing the Bridge PCIEBAR_0 with address 0x20000000_ABCDFFF4 on the bus for PCIe yields 0x1234_7FF4 on the AXI bus.

Figure 3-8: PCIe to AXI Translation

X-Ref Target - Figure 3-8

pg055_example2_address_translation_c_x12305.jpg

Accessing Bridge PCIEBAR_ 1 with address 0xA00000001235FEDC on the bus for PCIe yields 0xFE35FEDC on the AXI bus.