Enhanced Configuration Access - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

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2.9 English

When the AXI Memory Mapped to PCI Express core is configured as a Root Port, configuration traffic is generated by using the PCI Express Enhanced Configuration Access Mechanism (ECAM). ECAM functionality is available only when the core is configured as a Root Port. Reads and writes to a certain memory aperture are translated to configuration reads and writes, as specified in the PCI Express Base Specification ( v1.1 and v2.1 ), §7.2.2 [Ref 8] .

Depending on the core configuration, the ECAM memory aperture is 2 21 –2 28 (byte) addresses. The address breakdown is defined in Table: ECAM Addressing . The ECAM window begins at memory map base address and extends to 2 (20+ECAM_SIZE) - 1. ECAM_SIZE is calculated from the C_BASEADDR and C_HIGHADDR parameters. The number N of low-order bits of the two parameters that do not match, specifies the 2 n byte address range of the ECAM space. If C_INCLUDE_RC = 0, then ECAM_SIZE = 0.

When an ECAM access is attempted to the primary bus number, which defaults as bus 0 from reset, then access to the type 1 PCI™ Configuration Header of the integrated block in the Enhanced Interface for PCIe is performed. When an ECAM access is attempted to the secondary bus number, then type 0 configuration transactions are generated. When an ECAM access is attempted to a bus number that is in the range defined by the secondary bus number and subordinate bus number (not including the secondary bus number), then type 1 configuration transactions are generated. The primary, secondary, and subordinate bus numbers are written by Root Port software to the type 1 PCI Configuration Header of the Enhanced Interface for PCIe in the beginning of the enumeration procedure.

When an ECAM access is attempted to a bus number that is out of the bus_number and subordinate bus number, the bridge does not generate a configuration request and signal SLVERR response on the AXI4-Lite bus. When the AXI Memory Mapped to PCI Express is configured for EP ( C_INCLUDE_RC = 0 ), the underlying Integrated Block configuration space and the core memory map are available at the beginning of the memory space. The memory space looks like a simple PCI Express configuration space. When the AXI Memory Mapped to PCI Express is configured for RC ( C_INCLUDE_RC = 1 ), the same is true, but it also looks like an ECAM access to primary bus, Device 0, Function 0.

When the AXI Memory Mapped to PCI Express core is configured as a Root Port, the reads and writes of the local ECAM are Bus 0. Because the FPGA only has a single Integrated Block for PCIe core, all local ECAM operations to Bus 0 return the ECAM data for Device 0, Function 0.

Configuration write accesses across the PCI Express bus are non-posted writes and block the AXI4-Lite interface while they are in progress. Because of this, system software is not able to service an interrupt if one were to occur. However, interrupts due to abnormal terminations of configuration transactions can generate interrupts. ECAM read transactions block subsequent Requester read TLPs until the configuration read completions packet is returned to allow unique identification of the completion packet.

Table 2-24: ECAM Addressing





Byte Address

Ignored for this implementation. The S_AXI_CTL_WSTRB[3:0] signals define byte enables for ECAM accesses.


Register Number

Register within the configuration space to access.


Extended Register Number

Along with Register Number, allows access to PCI Express Extended Configuration Space.


Function Number

Function Number to completer.


Device Number

Device Number to completer.

(20+n-1) :20

Bus Number

Bus Number , 1 <= n <= 8. n is the number of bits available for Bus Number as derived from core parameters C_INCLUDE_RC, C_BASEADDR, and C_HIGHADDR .