Endpoint Model Test Bench for Root Port - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
Release Date
2.9 English

The Endpoint model test bench for the AXI Memory Mapped to PCI Express core in Root Port configuration is a simple example test bench that connects the Configurator example design and the PCI Express Endpoint model allowing the two to operate like two devices in a physical system. Because the Configurator example design consists of logic that initializes itself and generates and consumes bus traffic, the example test bench only implements logic to monitor the operation of the system and terminate the simulation.

The Endpoint model test bench consists of:

Verilog source code for all Endpoint model components

PIO slave design

Figure 6-2: Endpoint Model for AXI_PCIE Root Port

X-Ref Target - Figure 6-2