Enable External PIPE Interface - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

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2.9 English

When selected, this option enables an external third-party bus functional Model (BFM) to connect to the PIPE interface of the AXI PCIe core. Note that this option is disabled by default and is enabled when the Include Shared Logic (Clocking) in example design option is selected in the Shared Logic page of the Vivado IDE. This is applicable for both Endpoint and Root Port configurations.