Design Flow Steps - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

This chapter describes customizing and generating the core, constraining the core, and the simulation, synthesis and implementation steps that are specific to this IP core. More detailed information about the Vivado™ design flows and the Vivado IP integrator can be found in the following Vivado Design Suite user guides:

Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 15]

Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 12]

Vivado Design Suite User Guide: Getting Started (UG910) [Ref 11]

Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 13]