Clocking Interface - 2.9 English

clk_pclk

Input

Parallel clock used to synchronize data transfers across the parallel interface of the transceiver.

clk_rxusrclk

Input

Clock for the internal RX PCS datapath of the transceiver.

clk_fab_refclk

Input

Reserved.

clk_dclk

Input

GT DRP clock input. This clock is required for proper core operation even when GT DRP interface is not used by the user.

clk_userclk1 ⁽¹⁾

Input

Clock used internally for PCIe block logic.

clk_userclk2 ⁽¹⁾

Input

User clock used for the majority portion of the AXI-PCIe Bridge, AXI4 (axi_aclk_out), and AXI4-Lite (axi_ctl_aclk_out) interfaces.

clk_oobclk_in

Input

Free running clock used for OOB detect circuitry in the Transceivers

clk_mmcm_lock

Input

Indicates if the MMCM is locked onto the source clk. This signal is used only when external shared clocking logic is enabled.

clk_txoutclk

Output

Recommended clock output to the FPGA logic. Frequency of this clock will be equal to the sys_clk frequency.

clk_rxoutclk

Output

Reserved.

clk_pclk_sel

Output

Parallel clock select. This signal toggles when PCIe link up-trains to Gen2 speed.

clk_gen3

Output

Reserved.

pipe_mmcm_rst_n

Input

MMCM reset port. This port could be used by the upper layer to reset MMCM if error recovery is required. If the system detects the deassertion of MMCM lock, AMD recommends that you reset the MMCM. The recommended approach is to reset the MMCM after the MMCM input clock recovers (if MMCM reset occurs before the input reference clock recovers, the MMCM might never relock). After MMCM is reset, wait for MMCM to lock and then reset the PIPE Wrapper as normally done. Currently this port is tied High.

Notes:

1. clk_userclk1 and clk_userclk2 are the user clocks for PCIe and AXI related logic and are different than TX/RXUSRCLK and TX/RXUSRCLK2 referred in 7-series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 3] .
TX/RXUSRCLK and TX/RXUSRCLK2 referred there are 'user clocks' from the Transceivers perspective which are clk_pclk (Parallel clock).