This Figure shows the clocking diagram for the core. The main memory mapped AXI4 bus clock axi_aclk is driven by axi_aclk_out .
IMPORTANT: axi_aclk_out and axi_ctl_aclk_out are internally connected to axi_aclk and axi_ctl_aclk , respectively, and they do not need to be connected in the design.
The refclk input is used to generate the internal clocks used by the core and the output clocks . This clock must be provided at the reference clock frequency selected in the Vivado Integrated Design Environment (IDE) during IP generation.
The AXI4-Lite interconnect clock axi_ctl_aclk is driven by axi_ctl_aclk_out . The axi_ctl_aclk_out clock is rising edge aligned and an integer division of the axi_aclk_out clock.
The output clock frequency is either 62.5 MHz or 125 MHz depending on the PCIe link speed and link width and device selection.