Clock Debug - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
Release Date
2.9 English

One reason to not deassert the user_reset_out signal is that the FPGA PLL (MMCM) and Transceiver PLL have not locked to the incoming clock. To verify lock, monitor the transceiver RXPLLLKDET output and the MMCM LOCK output. If the PLLs do not lock as expected, it is necessary to ensure the incoming reference clock meets the requirements in 7 Series FPGAs GTX/GTH Transceivers User Guide [Ref 3] . The REFCLK signal should be routed to the dedicated reference clock input pins on the serial transceiver, and the design should instantiate the IBUFDS_GTE2 primitive in the design. See the 7 Series FPGAs GTX/GTH Transceivers User Guide for more information on PCB layout requirements, including reference clock requirements.

Reference clock jitter can potentially close both the TX and RX eyes, depending on the frequency content of the phase jitter. Therefore, maintain as clean a reference clock as possible. Reduce crosstalk on REFCLK by isolating the clock signal from nearby high-speed traces. Maintain a separation of at least 25 mils from the nearest aggressor signals.

The PCI Special Interest Group website provides other tools for ensuring the reference clocks are compliant to the requirements of the PCI Express Specification : .