Bus Location Register (Offset 0x140) - 2.9 English

Bus Location Register (Offset 0x140) - 2.9 English - PG055

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID

PG055

Release Date

2023-11-24

Version

2.9 English

The Bus Location register reports the Bus, Device, and Function number, and the Port number for the PCIe port ( Table: Bus Location Register ).

Table 2-12: Bus Location Register
Bits	Name	Core Access	Description
2:0	Function Number	RO	Function number of the port for PCIe. Hard-wired to 0.
7:3	Device Number	RO	Device number of port for PCIe. For Endpoint, this register is RO and is set by the Root Port.
15:8	Bus Number	RO	Bus number of port for PCIe. For Endpoint, this register is RO and is set by the external Root Port.
23:16	Port Number	RW	Sets the Port number field of the Link Capabilities register. EP: Read Only on all devices except for Spartan-6 FPGA. RP: Read and writeable.
31:24	Reserved	RO	Reserved