The Bus Location register reports the Bus, Device, and Function number, and the Port number for the PCIe port (
Table: Bus Location Register
).
Table 2-12:
Bus Location Register
|
Bits
|
Name
|
Core Access
|
Reset
Value
|
Description
|
|
2:0
|
Function Number
|
RO
|
0
|
Function number of the port for PCIe. Hard-wired to 0.
|
|
7:3
|
Device Number
|
RO
|
0
|
Device number of port for PCIe. For Endpoint, this register is RO and is set by the Root Port.
|
|
15:8
|
Bus Number
|
RO
|
0
|
Bus number of port for PCIe. For Endpoint, this register is RO and is set by the external Root Port.
|
|
23:16
|
Port Number
|
RW
|
0
|
Sets the Port number field of the Link Capabilities register. EP:
Read Only on all devices except for Spartan-6 FPGA.
RP:
Read and writeable.
|
|
31:24
|
Reserved
|
RO
|
0
|
Reserved
|