The Bridge Status and Control register (described in
Table: Bridge Status and Control Register
) provides information about the current state of the AXI4-Stream Bridge. It also provides control over how reads and writes to the Core Configuration Access aperture are handled.
Table 2-9:
Bridge Status and Control Register
|
Bits
|
Name
|
Core Access
|
Reset Value
|
Description
|
|
0
|
ECAM Busy
|
RO
|
0
|
Indicates an ECAM access is in progress (waiting for completion). This bit is tied to 0.
|
|
7:
1
|
Reserved
|
RO
|
0
|
Reserved
|
|
8
|
Global
Disable
|
RW
|
0
|
When set, disables interrupt line from being asserted. Does not prevent bits in Interrupt Decode register from being set.
|
|
15:9
|
Reserved
|
RO
|
0
|
Reserved
|
|
16
|
RW1C as RW
|
RW
|
0
|
When set, allows writing to core registers which are normally RW1C.
|
|
17
|
RO as RW
|
RW
|
0
|
When set, allows writing to certain registers which are normally RO.
(Only supported for 7-series and Zynq 7000 SoC device cores.)
|
|
31:
18
|
Reserved
|
RO
|
0
|
Reserved
|