Bridge Parameters - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

Because many features in the AXI Memory Mapped to PCI Express core design can be parameterized, you can uniquely tailor the implementation of the core using only the resources required for the desired functionality. This approach also achieves the best possible performance with the lowest resource usage.

The parameters defined for the AXI Memory Mapped to PCI Express are shown in Table: Top-Level Parameters .

Table 2-2: Top-Level Parameters

Generic

Parameter Name

Description

Allowable Values

Default Value

VHDL Type

Bridge Parameters

C_ PCIE_BLK_LOCN

PCIe integrated block location within FPGA

0: X0Y0

1: X0Y1

2: X0Y2

3: X1Y0

4: X1Y1

0

String

C_XLNX_REF_BOARD

Target FPGA Board

NONE

KC705_REVA

KC705_REVB

KC705_REVC

VC707

NONE

String

G1

C_FAMILY

Target FPGA Family

kintex7, virtex7, artix7, zynq

String

G2

C_INCLUDE_RC

Configures the AXI bridge for PCIe to be a Root Port or an Endpoint

0: Endpoint
1: Root Port (applies only for 7 series, and Zynq 7000 SoC devices)

0

Integer

G3

C_COMP_TIMEOUT

Selects the slave bridge completion timeout counter value

0: 50 ┬Ás
1: 50 ms

0

Integer

G4

C_INCLUDE_
BAROFFSET_REG

Include the registers for high-order bits to be substituted in translation in slave bridge

0: Exclude
1: Include

0

Integer

G5

C_SUPPORTS_
NARROW_BURST

Instantiates internal logic to support narrow burst transfers. Only enable when AXI master bridge generates narrow burst traffic.

0: Not supported
1: Supported

0

Integer

G6

C_AXIBAR_NUM

Number of AXI address apertures that can be accessed

1: BAR_0 enabled

2: BAR_0, BAR_1 enabled

3: BAR_0, BAR_1, BAR_2 enabled

4: BAR_0 through BAR_3 enabled

5: BAR_0 through BAR_4 enabled

6: BAR_0 through BAR_5 enabled

6

Integer

G7

C_AXIBAR_0

AXI BAR_0 aperture low address

Valid AXI address (1) (3) (4)

0xFFFF_FFFF

std_logic_
vector

G8

C_AXIBAR_
HIGHADDR_0

AXI BAR_0 aperture high address

Valid AXI address (1) (3) (4)

0x0000_0000

std_logic_
vector

G9

C_AXIBAR_AS_0

AXI BAR_0 address size

0: 32 bit

1: 64 bit

0

Integer

G10

C_AXIBAR2PCIEBAR_0

Initial address translation from an AXI BAR_0 address to a PCI Express address

Valid address for PCIe (2)

0xFFFF_FFFF

std_logic_
vector

G11

C_AXIBAR_1

AXI BAR_1 aperture low address

Valid AXI address (1) (3) (4)

0xFFFF_FFFF

std_logic_
vector

G12

C_AXIBAR_
HIGHADDR_1

AXI BAR_1 aperture high address

Valid AXI address (1) (3) (4)

0x0000_0000

std_logic_
vector

G13

C_AXIBAR_AS_1

AXI BAR_1 address size

0: 32 bit

1: 64 bit

0

Integer

G14

C_AXIBAR2PCIEBAR_1

Initial address translation from an AXI BAR_1 address to a PCI Express address

Valid address for PCIe (2)

0xFFFF_FFFF

std_logic_
vector

G15

C_AXIBAR_2

AXI BAR_2 aperture low address

Valid AXI address (1) (3) (4)

0xFFFF_FFFF

std_logic_
vector

G16

C_AXIBAR_
HIGHADDR_2

AXI BAR_2 aperture high address

Valid AXI address (1) (3) (4)

0x0000_0000

std_logic_
vector

G17

C_AXIBAR_AS_2

AXI BAR_2 address size

0: 32 bit

1: 64 bit

0

Integer

G18

C_AXIBAR2PCIEBAR_2

Initial address translation from an AXI BAR_2 address to a PCI Express address

Valid address for PCIe (2)

0xFFFF_FFFF

std_logic_
vector

G19

C_AXIBAR_3

AXI BAR_3 aperture low address

Valid AXI address (1) (3) (4)

0xFFFF_FFFF

std_logic_
vector

G20

C_AXIBAR_
HIGHADDR_3

AXI BAR_3 aperture high address

Valid AXI address (1) (3) (4)

0x0000_0000

std_logic_
vector

G21

C_AXIBAR_AS_3

AXI BAR_3 address size

0: 32 bit

1: 64 bit

0

Integer

G22

C_AXIBAR2PCIEBAR_3

Initial address translation from an AXI BAR_3 address to a PCI Express address

Valid address for PCIe (2)

0xFFFF_FFFF

std_logic_
vector

G23

C_AXIBAR_4

AXI BAR_4 aperture low address

Valid AXI address (1) (3) (4)

0xFFFF_FFFF

std_logic_
vector

G24

C_AXIBAR_
HIGHADDR_4

AXI BAR_4 aperture high address

Valid AXI address (1) (3) (4)

0x0000_0000

std_logic_
vector

G25

C_AXIBAR_AS_4

AXI BAR_4 address size

0: 32 bit

1: 64 bit

0

Integer

G26

C_AXIBAR2PCIEBAR_4

Initial address translation from an AXI BAR_4 address to a PCI Express address

Valid address for PCIe (2)

0xFFFF_FFFF

std_logic_
vector

G27

C_AXIBAR_5

AXI BAR_5 aperture low address

Valid AXI address (1) (3) (4)

0xFFFF_FFFF

std_logic_
vector

G28

C_AXIBAR_
HIGHADDR_5

AXI BAR_5 aperture high address

Valid AXI address (1) (3) (4)

0x0000_0000

std_logic_
vector

G29

C_AXIBAR_AS_5

AXI BAR_5 address size

0: 32 bit

1: 64 bit

0

Integer

G30

C_AXIBAR2PCIEBAR_5

Initial address translation from an AXI BAR_5 address to a PCI Express address

Valid address for PCIe (2)

0xFFFF_FFFF

std_logic_
vector

G31

C_PCIEBAR_NUM

Number of address for PCIe apertures that can be accessed

1: BAR_0 enabled

2: BAR_0, BAR_1 enabled

3: BAR_0, BAR_1, BAR_2 enabled

3

Integer

G32

C_PCIEBAR_AS

Configures PCIEBAR aperture width to be 32 bits wide or 64 bits wide

0: Generates three 32-bit PCIEBAR address apertures.

32-bit BAR example:

PCIEBAR_0 is 32 bits

PCIEBAR_1 is 32 bits

PCIEBAR_2 is 32 bits

1: Generates three 64 bit PCIEBAR address apertures.

64-bit BAR example:

PCIEBAR_0 and PCIEBAR_1 concatenate to comprise 64-bit PCIEBAR_0.

PCIEBAR_2 and PCIEBAR_3 concatenate to comprise 64-bit PCIEBAR_1.

PCIEBAR_4 and PCIEBAR_5 concatenate to comprise 64-bit PCIEBAR_2

1

Integer

G33

C_PCIEBAR_LEN_0

Specifies the size of the PCIe BAR

13-31

16

Integer

G34

C_PCIEBAR2AXIBAR_0

Initial address translation from an AXI BAR_0 address to a PCI Express address

Valid AXI address

0x0000_0000

std_logic_
vector

C_PCIEBAR2AXIBAR_0_SEC

Defines the AXIBAR memory space (PCIe BAR_0) (accessible from PCIe) to be either secure or non-secure memory mapped.

0: Denotes a non-secure memory space

1: Marks the AXI memory space as secure

0

Integer

G35

C_PCIEBAR_LEN_1

Specifies the size of the PCIe BAR.

13-31

16

Integer

G36

C_PCIEBAR2AXIBAR_1

Initial address translation from an AXI BAR_1 address to a PCI Express address

Valid AXI address

0x0000_0000

std_logic_
vector

G37

C_PCIEBAR_LEN_2

Specifies the size of the PCIe BAR.

13-31

16

Integer

G38

C_PCIEBAR2AXIBAR_2

Initial address translation from an AXI BAR_2 address to a PCI Express address.

Valid AXI address

0x0000_0000

std_logic_
vector

C_PCIEBAR2AXIBAR_2_SEC

Defines the AXIBAR memory space (PCIe BAR_2) (accessible from PCIe) to be either secure or non-secure memory mapped.

0: Denotes a non-secure memory space

1: Marks the AXI memory space as secure

0

Integer

AXI4-Lite Parameters

G39

C_BASEADDR

Device base address

Note: When configured as an RP, the minimum alignment granularity must be 256 MB. Bit [27:0] are used for Bus Number, Device Number, Function number.

Valid AXI address

0xFFFF_FFFF

std_logic_
vector

G40

C_HIGHADDR

Device high address

Valid AXI address

0x0000_0000

std_logic_
vector

C_S_AXI_CTL_
PROTOCOL

AXI4-Lite port connection definition to AXI Interconnect in the Vivado IP integrator.

AXI4LITE

AXI4LITE

String

Core for PCIe Configuration Parameters

G41

C_NO_OF_LANES

Number of PCIe Lanes

1, 2, 4, 8: 7 series FPGAs

1

Integer

G42

C_DEVICE_ID

Device ID

16-bit vector

0x0000

std_logic_
vector

G43

C_VENDOR_ID

Vendor ID

16-bit vector

0x0000

std_logic_
vector

G44

C_CLASS_CODE

Class Code

24-bit vector

0x00_0000

std_logic_
vector

G45

C_REV_ID

Rev ID

8-bit vector

0x00

std_logic_
vector

G46

C_SUBSYSTEM_ID

Subsystem ID

16-bit vector

0x0000

std_logic_
vector

G47

C_SUBSYSTEM_
VENDOR_ID

Subsystem Vendor ID

16-bit vector

0x0000

std_logic_
vector

C_PCIE_USE_MODE

Specifies PCIe use mode for underlying serial transceiver wrapper usage/configuration (specific only to 7 series).

This parameter ignored for Zynq 7000 SoC devices (set to 3.0).

See Table: Silicon Version Specification .

1.0: For Kintex 7 325T IES (initial ES) silicon

1.1: For Virtex 7 485T IES (initial ES) silicon

3.0: For GES (general ES) silicon

1.0

String

G48

C_PCIE_CAP_SLOT_
IMPLEMENTED

PCIE Capabilities

Register Slot

Implemented

0: No add-in card slot
1: Downstream port is connected to add-in card slot
(valid only for Root

Complex)

0

Integer

G49

C_REF_CLK_FREQ

REFCLK input

Frequency

0: 100 MHz

1: 125 MHz

2: 250 MHz - 7 series FPGAs only

0

Integer

C_NUM_MSI_REQ

Specifies the size of the MSI request vector for selecting the number of requested message values.

0-5

0

Integer

Memory Mapped AXI4 Parameters

G50

C_M_AXI_DATA_
WIDTH

AXI Master Bus Data width

64: 7 series FPGAs only
128: 7 series FPGAs only

64

Integer

G51

C_M_AXI_ADDR_
WIDTH

AXI Master Bus Address width

32

32

Integer

G52

C_S_AXI_ID_WIDTH

AXI Slave Bus ID width

4

4

Integer

G53

C_S_AXI_DATA_
WIDTH

AXI Slave Bus Data width

64: 7 series FPGAs only
128: 7 series FPGAs only

64

Integer

G54

C_S_AXI_ADDR_
WIDTH

AXI Slave Bus Address width

32

32

Integer

G55

C_MAX_LINK_
SPEED

Maximum PCIe link speed supported

0: 2.5 GT/s - 7 series

1: 5.0 GT/s - 7 series

0

Integer

G56

C_INTERRUPT_PIN

Legacy INTX pin support/select

0: No INTX support (setting for Root Port)

1: INTA selected (only allowable when core in Endpoint configuration)

0

Integer

AXI4 Slave Interconnect Parameters (6)

G57

NUM_WRITE_
OUTSTANDING

AXI Interconnect Slave Port Write Pipeline Depth

1: Only one active AXI AWADDR can be accepted in the AXI slave bridge for PCIe

2: Maximum of two active AXI AWADDR values can be stored in AXI slave bridge for PCIe

2

Integer

G58

NUM_READ_
OUTSTANDING

AXI Interconnect Slave Port Read Pipeline Depth

1: Only one active AXI ARADDR can be accepted in AXI slave bridge PCIe.

2, 4, 8: Size of pipeline for active AXI ARADDR values to be stored in AXI slave bridge PCIe

A value of 8 is not allowed for 128-bit core (Gen2 7 series) configurations. The maximum setting of this parameter value is 4.

8

Integer

AXI4 Master Interconnect Parameters

G59

NUM_WRITE_
OUTSTANDING

AXI Interconnect master bridge write address issue depth

1, 2, 4: Number of actively issued AXI AWADDR values on the AXI Interconnect to the target slave device(s).

4

Integer

G60

NUM_READ_
OUTSTANDING

AXI Interconnect master bridge read address issue depth

1, 2, 4: Number of actively issued AXI ARADDR values on the AXI Interconnect to the target slave device(s).

4

Integer

Notes:

1. This is a 32-bit address.

2. The width of this should match the address size (C_AXIBAR_AS) for this BAR.

3. The range specified must comprise a complete, contiguous power of two range, such that the range = 2 n and the n least significant bits of the Base Address are zero. The address value is a 32-bit AXI address.

4. The difference between C_AXIBAR_n and C_AXIBAR_HIGHADDR_n must be less than or equal to 0x7FFF_FFFF and greater than or equal to 0x0000_1FFF.

5. It is recommended that you do not edit these default values on the AXI Memory Mapped to PCI Express IP unless you need to reduce the resource utilization. Doing so impacts the AXI bridge performance.

6. These are the user parameters of the AXI4 Interconnect. By default, the slave bridge handles up to two AXI4 write requests and eight AXI4 read requests. The master bridge handles up to four PCIe write/read requests.