The Bridge Info register (described in
Table: Bridge Info Register
) provides general configuration information about the AXI4-Stream Bridge. Information in this register is static and does not change during operation.
Table 2-8:
Bridge Info Register
|
Bits
|
Name
|
Core Access
|
Reset
Value
|
Description
|
|
0
|
Gen2 Capable
|
RO
|
0
|
If set, underlying integrated block supports PCIe Gen2 speed.
|
|
1
|
Root Port Present
|
RO
|
0
|
Indicates the underlying integrated block is a Root Port when this bit is set.
If set, Root Port registers are present in this interface.
|
|
2
|
Up Config Capable
|
RO
|
|
Indicates the underlying integrated block is upconfig capable when this bit is set.
|
|
15:3
|
Reserved
|
RO
|
0
|
Reserved
|
|
18:16
|
ECAM Size
|
RO
|
0
|
Size of Enhanced Configuration Access Mechanism (ECAM) Bus Number field, in number of bits. If ECAM window is present, value is between 1 and 8. If not present, value is 0. Total address bits dedicated to ECAM window is 20+(ECAM Size).
The size of the ECAM is determined by the parameter settings of C_BASEADDR and C_HIGHADDR.
|
|
31:
19
|
Reserved
|
RO
|
0
|
Reserved
|