Base Address Register Overview - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

The AXI Memory Mapped to PCI Express core in Endpoint configuration supports up to three 32-bit BARs or three 64-bit BARs. The AXI Memory Mapped to PCI Express in Root Port configuration supports one 32-bit BARs or one 64-bit BAR.

All BAR registers share these options:

Checkbox : Click the checkbox to enable BAR. Deselect the checkbox to disable BAR.

Type : BARs can be Memory apertures only. Memory BARs can be either 64-bit or 32-bit. Prefetch is enabled for 64-bit and not enabled for 32-bit. When a BAR is set as 64 bits, it uses the next BAR for the extended address space, making it inaccessible.

Size : The available Size range depends on the PCIe ® Device/Port Type and the Type of BAR selected. Table: BAR Size Ranges for Device Configuration lists the available BAR size ranges.

Table 4-3: BAR Size Ranges for Device Configuration

PCIe Device/Port Type

BAR Type

BAR Size Range

PCI Express Endpoint

32-bit Memory

8 KB - 2 GB

64-bit Memory

8 KB - 2 GB

Root Port of PCI Express Root Complex

32-bit Memory

8 KB - 2 GB

64-bit Memory

8 KB - 4 GB

Value : The value assigned to BAR based on the current selections.

PCIe to AXI Translation : This text field should be set to the appropriate value to perform the translation from the PCI Express base address to the desired AXI Base Address.

For more information about managing the Base Address Register settings, see Managing Base Address Register Settings .