BAR Addressing - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

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2.9 English

C_AXIBAR_n and C_AXIBAR_HIGHADDR_n are used to calculate the size of the AXI BAR n and during address translation to PCIe address.

C_AXIBAR_n provides the low address where AXI BAR n starts and will be regarded as address offset 0x0 when the address is translated.

C_AXIBAR_HIGHADDR_n is the high address of the last valid byte address of AXI BAR n. (For more details on how the address gets translated, see Address Translation .)

The difference between the two parameters are your AXI BAR n size. These parameters must be set accordingly such that AXI BAR n size is a power of two and must have at least 8 KB and a maximum of 2 GB.

When a packet is sent to the core (outgoing PCIe packets), the packet must have an address that is in the range of C_AXIBAR_n and C_AXIBAR_HIGHADDR_n. Any packet that is received by the core that has an address outside of this range will be responded to with a SLVERR (Slave Error). When IP Integrator is used, these parameters are derived from the Address Editor tab within IP Integrator. The Address Editor sets the AXI Interconnect as well as the core so the address range matches, and the packet is routed to the core only when the packet has an address within the valid range.