Architecture - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

The Endpoint model consists of these blocks:

PCI Express Endpoint ( AXI Memory Mapped to PCI Express in Endpoint configuration) model.

PIO slave design, consisting of:

° pio_rx_engine

° pio_tx_engine

° pio_ep_mem

° pio_to_ctrl

The pio_rx_engine and pio_tx_engine blocks interface with the ep block for reception and transmission of TLPs from/to the Root Port Design Under Test (DUT). The Root Port DUT consists of the core configured as a Root Port and the Block RAM controller along with s_axi and s_axi_ctl models to drive traffic on s_axi and s_axi_ctl .