Add. Debug Options - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

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2.9 English

This Figure consists of an option to enable the JTAG debugger for debugging purpose.

Figure 4-8: Add. Debug Options

X-Ref Target - Figure 4-8


The feature provides debug usability for the following:

Option to integrate PCIe debug options in the IP core top which is needed to be included in the user design.

Assumes an external clock to be used.

LTSSM State Transitions : This shows all the LTSSM state transitions that have been made starting from link-up.

PHY Reset FSM Transitions : This shows the PHY reset FSM (internal state machine that is used by the PCIe solution IP).

Receiver Detect : This shows all the lanes that have completed Receiver Detect successfully.

The following are the steps:

1. Open a new Vivado Design Suite and connect to the board.

2. The hw_axi_1 should be present.

Figure 4-9: hw_axi_1 Location

X-Ref Target - Figure 4-9


3. Type source test_rd.tcl in the Vivado Tcl Console.

4. For post-processing, double-click the following:

° draw_ltssm.tcl (Windows) or wish draw_ltssm.tcl

° draw_reset.tcl (Windows) or wish draw_reset.tcl

° draw_rxdet.tcl (Windows) or wish draw_rxdet.tcl

This displays the pictorial representation of the LTSSM state transitions.