This section describes how the Slave side ( Table: Slave Bridge Response to Abnormal Conditions ) and Master side ( Table: Master Bridge Response to Abnormal Conditions ) of the AXI Memory Mapped to PCI Express core handle abnormal conditions.
This section describes how the Slave side ( Table: Slave Bridge Response to Abnormal Conditions ) and Master side ( Table: Master Bridge Response to Abnormal Conditions ) of the AXI Memory Mapped to PCI Express core handle abnormal conditions.