AXI4-Lite Interfaces - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

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2.9 English

Read from a register that does not have all 0s as a default to verify that the interface is functional. Output s_axi_arready asserts when the read address is valid and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive ensure that the following conditions are met.

The axi_ctl_aclk and axi_ctl_aclk_out clock inputs are connected and toggling.

The interface is not being held in reset, and axi_aresetn is an active-Low reset.

Ensure that the main core clocks are toggling and that the enables are also asserted.

Has a simulation been run? Verify in simulation and/or a Vivado Design Suite debug feature capture that the waveform is correct for accessing the AXI4-Lite interface.