AXI Transactions for PCIe - 2.9 English - PG055

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)
Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

Table: AXI4 Memory-Mapped Transactions to AXI4-Stream PCIe TLPs and Table: AXI4-Stream PCIe TLPs to AXI4 Memory Mapped Transactions are the translation tables for AXI4-Stream and memory-mapped transactions.

Table 3-3: AXI4 Memory-Mapped Transactions to AXI4-Stream PCIe TLPs

AXI4 Memory-Mapped Transaction

AXI4-Stream PCIe TLPs

INCR Burst Read of 32-bit address AXIBAR

MemRd 32 (3DW)

INCR Burst Write to 32-bit address AXIBAR

MemWr 32 (3DW)

INCR Burst Read of 32-bit address AXIBAR

MemRd 64 (4DW)

INCR Burst Write to 32-bit address AXIBAR

MemWr 64 (4DW)

Table 3-4: AXI4-Stream PCIe TLPs to AXI4 Memory Mapped Transactions

AXI4-Stream PCIe TLPs

AXI4 Memory-Mapped Transaction

MemRd 32 (3DW) of PCIEBAR

INCR Burst Read with 32-bit address

MemWr 32 (3DW) to PCIEBAR

INCR Burst Write with 32-bit address

MemRd 64 (4DW) of PCIEBAR

INCR Burst Read with 32-bit address

MemWr 64 (4DW) to PCIEBAR

INCR Burst Write with 32-bit address

Note: s_axi_wstrb can be used to facilitate data alignment to an address boundary. s_axi_wstrb may equal to 0 in the beginning of valid data cycle and will appropriately calculate an offset to the given address. However, the valid data identified by s_axi_wstrb must be continuous from the first byte enable to the last byte enable.