Minimum Device Requirements - Minimum Device Requirements - 3.3 English - PG054

7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054)
Document ID
PG054
Release Date
2024-12-06
Version
3.3 English

The following table lists the minimum device requirements for 7 Series Integrated Block for PCIe configurations.

Table 1. Core Configurations
  Zynq 7000 Devices Vitex 7 FPGAs Kintex 7 FPGAs Artix 7 FPGAs 5

ZC7012

ZC7012S

ZC70151

ZC7030 2

ZC7035 3

ZC7045 3

ZC7100 3

XC7VX485T XC7V585T XC7V2000T

XC7K325T

XC7K355T

XC7K410T

XC7K420

XC7K480T

XCK7160T 4

XC7K70T 4

XC7A12T

XC7A15T

XC7A25T

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

Number of Integrated Blocks for PCIe Available Integrated Blocks for PCIe 1 4 3 4 6 1 1
Lanes Gen1 (2.5 Gb/s) 1-4 or 1-8 1–8 1–8 1–8 1–8 1–4 7
Gen2 (5.0 Gb/s) 1-4 or 1-8 1–8 1–8 1–8 1–8 1–4 7
Gen3 (8.0 Gb/s) 8 — — — — — —
Speed Grade x1–x4 Gen1 -1, -2, -3, -2L, -1L -1, -2, -3, -2L -1, -2, -3, -2L -1, -2, -2L -1, -2, -3, -2L -1, -2, -3, -2L
x8 Gen1 -1, -2, -3, -2L, -1L -1, -2, -3, -2L -1, -2, -3, -2L -1, -2, -2L -1, -2, -3, -2L NA
x1–x4 Gen2 -1, -2, -3, -2L (1V) -1, -2, -3, -2L (1V) -1, -2, -3, -2L (1V) -1, -2, -2L (1V) -1, -2, -3, -2L (1V) 12 -2, -3 (1V)
x8 Gen2 -2, -3, -2L (1V) -2, -3, -2L (1V) -2, -3, -2L (1V) -2, -2L (1V) -2, -3, -2L (1V) 12 NA
Maximum Payload Size MPS (Bytes) Gen1 1024 1024 1024 1024 1024 1024
x1–x4 Gen2 1024 1024 1024 1024 1024 1024
x8 Gen2

512 (-3)

256 (-2, -2L (1V)) 11

512 (-3) 256 (-2, -2L (1V)) 512 (-3) 256 (-2,-2L(1V)) 512 (-3) 256 (-2, -2L(1V)) 512 (-3) 256 (-2, -2L (1V)) N/A
  1. ZC7015 and ZC7012S device supports only up to Gen1 speed for -1 speed grades. For other speed grades, the maximum link speed supported is Gen2 and link width is x4.
  2. ZC7030 device supports max link width up to x4 and link speed Gen2.
  3. ZC7035,ZC7045 and ZC7100 devices support maximum x8 link width and up to Gen2 link speed for speed grades other than -1. For speed grade -1, ZC7035,ZC7045 and ZC7100 devices supports Gen1 speed up to x8 link width and Gen2 speed up to x4 link width only.
  4. Kintex 7 FBG484 package supports only x1, x2, and x4 operation; x8 is not supported.
  5. Artix 7 devices only support x1, x2, and x4 operation.
  6. There are four integrated blocks in XC7V2000T; however, due to the lack of bonded transceivers, not all four can be used. See Available Integrated Blocks for PCIe for the number of blocks supported in specific packages.
  7. For the CPG236, CPG238 and XC7A12T-CSG325 packages, the maximum link width supported is x2 (Total Lanes 1-2).
  8. The 7 series FPGAs Integrated Block for PCI Express does not support the Gen3 operation. See Virtex 7 FPGA Gen3 Integrated Block for PCI Express Product Guide Virtex 7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023) for device support and information on the Virtex 7 FPGA Gen3 Integrated Block for PCI Express.
  9. 1-4 lanes for 7030 devices, and 1-8 lanes for 7045 devices.
  10. Not all SSI devices-PCIe/MMCM site pairs pass timing skew checks.
  11. This is the minimum supported speed grade for the specified MPS value.
  12. Gen2 line rate is not supported for -2L (0.9V).