The following table defines associated control register of the TX PTP Packet Buffers used by the software to request the transmission of the PTP frames.
| Bits | Default Value | Type | Description |
|---|---|---|---|
| 31:19 | 0 | RO | Reserved |
| 18:16 | 0 | RO | tx_packet. Indicates the number (block RAM bin position) of the most recently transmitted PTP packet. |
| 15:8 | 0 | RO |
tx_frame_waiting Indication. The TX PTP Packet Buffer is split into eight regions of 256 bytes, each of which can contain a separate PTP frame. There is one tx_frame_waiting bit for each of the eight regions. When logic is set as 1, each bit indicates that a request has been made for frame transmission to the TX Arbiter, but that a grant has not yet occurred. When the frame has been successfully transmitted, the bit is set to logic 0. This bit allows the microprocessor to run off a polling implementation as opposed to the Interrupts. |
| 7:0 | 0 | WO |
tx_send_frame Bits. The TX PTP Packet Buffer is split into eight regions of 256 bytes, each of which can contain a separate PTP frame. There is one tx_send_frame bit for each of the eight regions. When each bit is written to one, causes a request to be made to the TX Arbiter. When access is granted the frame contained within the respected region is transmitted. If read, always returns 0. |
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